1. Field of the Invention
This invention relates to a semiconductor device having a mesa groove and its manufacturing method. In this application, the semiconductor device having a mesa groove is named as a mesa type semiconductor device.
2. Description of the Related Art
A mesa type power diode has been known as one of the mesa type semiconductor devices. A mesa type diode according to a prior art is described referring to FIGS. 8 and 9. FIG. 8 is an outline plan view showing a semiconductor wafer in which a plurality of the mesa type diodes according to the prior art is arrayed in a matrix form. FIG. 9 is a cross-sectional view of a section X-X in FIG. 8, showing the wafer after being diced along scribe lines DL.
An N− type semiconductor layer 102 is formed on a surface of an N+ type semiconductor substrate 101. A first insulation film 105 is formed on a P type semiconductor layer 103 that is formed on a surface of the N− type semiconductor layer 102. There is formed an anode electrode 106 that is electrically connected with the P type semiconductor layer 103.
Also, there is formed a mesa groove 108 that extends from a surface of the P type semiconductor layer 103 to the N+ type semiconductor substrate 101. The mesa groove 108 penetrates through the N− type semiconductor layer 102, and its bottom is located inside the N+ type semiconductor substrate 101. Sidewalls of the mesa groove 108 are tapered down from the surface of the P type semiconductor layer 103 to the bottom of the mesa groove 108 to have a normal tapered shape. The mesa type diode is surrounded by the mesa groove 108 to have a mesa type structure.
A second insulation film 130 made of a polyimide film is formed to cover the sidewalls of the mesa groove 108, and a cathode electrode 107 is formed on a back surface of the N+ type semiconductor substrate 101.
The mesa type semiconductor device is described in Japanese Patent Application Publication No. 2003-347306, for example.
The second insulation film 130 in the conventional mesa type diode is shown in FIG. 9 to cover inner walls of the mesa groove 108 with a uniform thickness. In reality, however, the second insulation film 130 is thinner at upper portions of the inner walls of the mesa groove 108 and accumulates thicker at the bottom of the mesa groove 108, as shown in FIG. 11. The shape as described above is formed in following process steps. When the second insulation film 130 is provided into the mesa groove 108 by dispensing or the like, the mesa groove 108 is filled with the second insulation film 130, as shown in FIG. 10. Imidization reaction takes place during subsequent thermal treatment, and because of increased fluidity of the second insulation film 130, the second insulation film 130 as a whole flows toward the bottom of the mesa groove 108 to reduce the thickness of the second insulation film 130 at the upper portions of the inner walls of the mesa groove 108, as shown in FIG. 11.
As a result, the thickness of the second insulation film 130 is reduced at a mesa groove-side sidewall 110 corresponding to a PN junction PNJC where an electric field is most intense, causing serious problems to be solved such as deterioration in a withstand voltage of the PN junction and increase in a leakage current to reduce yield and reliability. As a method to solve the problems, it is conceivable that the second insulation film is formed repeatedly. However, this method increases a cost of the semiconductor device because a material of the second insulation film is expensive.